With the rapid development on the semiconductor process technology, the process node continues to shrink, and a gate-last process is widely used to obtain a desired threshold voltage and to improve the device performance. However, when the critical dimension (CD) is further reduced, the conventional structure of MOSFETs can no longer match the requirements of the desired device performance even when the gate-last process is used. Therefore, multiple-gate devices have attracted extensive attentions as the substitutes of the conventional devices.
The fin field-effect transistor (Fin FET) is a typical multiple-gate device. FIGS. 1-4 illustrate an existing fabrication process of a Fin FET.
As shown in FIG. 1, a semiconductor substrate 100 having a first region I and a second region II is provided. A first hard mask layer 101 is formed on one surface of the semiconductor substrate 100, and the first hard mask layer 101 in the second region II has a first opening 102. Then a first trench 103 is formed by etching a portion of the semiconductor substrate 100 corresponding to the first opening 102.
As shown in FIG. 2, a first isolation material (not shown) is formed onto the hard mask layer 101 to completely fill the first opening 102 and the first trench 103. Further, the first isolation material and the first mask 101 are removed by a chemical mechanical polishing (CMP) process using the surface of the semiconductor substrate 100 as a stop layer, i.e., the CMP process is stopped when it reaches the surface of the semiconductor substrate. Thus a first isolation structure 104 is formed to isolate adjacent source regions.
Further, as shown in FIG. 3, a second hard mask layer 105 is formed on the surface of the semiconductor substrate 100. The second hard mask layer has a plurality of second openings 106. Then an etching process is performed onto the semiconductor substrate 100 corresponding to the second openings 106, a plurality of fins 108 are thus formed. There are a plurality of second trenches 107 in between the adjacent fins 108 and also in between the fins 108 and the semiconductor substrate 100. The position of the second trenches is corresponding to the second openings 106, and the depth of the second trench 107 is smaller than the depth of the first trench 103.
And further, as shown in FIG. 4, a second isolation material (not shown) is formed onto the second hard mask layer 105. The second openings 106 and the second trenches 107 are completely filled. Further, a CMP process is performed to remove the second isolation material and the second mask layer 105; a plurality second isolation structure 109 are thus formed inside the second trenches 107 to electrically isolate the adjacent fins 108.
According to the described structure and fabrication process, the existing method for forming Fin FETs is relatively complex. For example, because the depth of the first isolation structure 104 is greater than the depth of the second isolation structure 109, in order to form the first isolation structure 104 and the second isolation structure 109, two separate hard mask layers, the first mask layer 101 and the second hard mask layer 105, are used. The disclosed device structures, methods and systems are directed to solve one or more problems set forth above and other problems.